List of  2020 B.Tech VLSI projects | Verilog

List of 2020 B.Tech VLSI projects | Verilog

We provide B.Tech VLSI projects (Verilog/Vhdl) simulation code with step by step explanation.

Explain methodically from the basic level to final results. Software install in students laptops and execute the code .

A RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
B A Cellular Network Architecture With Polynomial Weight Functions
C A Novel Implementation of QPSK Modulator on FPGA
D An Efficient Digital Baseband Encoder for Short Range Wireless Communication Applications
1. Vectored Implementation of Hierarchical 22n QAM
2. Normalized Subband Adaptive Filtering Algorithm with Reduced Computational Complexity
3. Low-Power Architecture for the Design of a One-Dimensional Median Filter
4 Area-Delay Efficient Binary Adders in QCA
5 Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells
6 Data encoding techniques for reducing energy Consumption in network-on-chip
7 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
8 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
9 Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes
10 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm
11 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
12 Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver
13 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator
14 VLSI implementation of a low cost and high quality image scaling processor
15 An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
16 Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement.
17 Low-Power and Area-Efficient Shift Register Using Pulsed Latches.
18 FPGA Implementation and Evaluation of Discrete-time Chaotic Generators Circuits
19 Result-Biased Distributed-Arithmetic-Based  Filter Architectures for Approximately Computing the DWT
20 Reconfigurable Filter Bank With Complete Control Over Sub band Bandwidths for Multi standard Wireless Communication Receivers
21 Efficient Parallel Architecture for Linear Feedback Shift Registers
22 Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data
23 VLSI based robust router architecture
24 Calculation of LFSR Seed and Polynomial Pair for BIST Applications

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